1. Field of the Invention
The present invention relates to a semiconductor memory, especially a dynamic random access memory (DRAM), and more particularly, the present invention relates to a series of cell structures, arrangements, and activation schemes for high density, low power semiconductor memories.
2. Description of the Background
A conventional DRAM memory cell, consisting of one transistor and one capacitor (referred to as a 1T-1C configuration), is commonly used as a semiconductor memory when high bit density is required. This technology has several drawbacks and faces serious complications as device dimensions are scaled smaller. Most notably, since the DRAM cell has no internal gain, a high capacitance element (xcx9c30 fF) must be fabricated in each cell to store a charge large enough to be adequately detected. Therefore, complex capacitor structures and expensive materials must be used to build a device with adequate capacitance, which leads to expensive fabrication and incompatibilities with standard logic processes.
In response to these limitations, small area gain cell memory technologies have been proposed. These are configured as 2- or 3-transistor cells in which a charge is stored in such a way that the conduction of a readout transistor is altered, thus providing internal gain. However, these technologies exhibit various problems that limit their widespread acceptance. Among these problems, cell size is still much larger than that of DRAM. This is due to the extra area used for additional transistors or spacing due to wire routing. For example, in many cells, two data and two word lines are necessary, limiting the cell size to twice the line pitch.
Other problems exhibited by gain cell technologies include short retention periods due to low storage capacitance and high leakage currents. In addition, driving and sensing schemes are often more complex than those found in conventional DRAM memories. Complex fabrication processes may be necessary for multi-transistor gain cells, further reducing the likelihood of their use as a replacement for DRAM.
According to at least one preferred embodiment of the present invention, a memory is provided comprising a plurality of memory cells, each containing a gain cell structure. Furthermore, the present invention comprises a method of writing information in which the stored charge on the storage node has an inverse relation to the voltage of the data line. Whereas in a conventional memory the storage node is connected to a write data line through a write transistor, according to the present method the node normally attached to a write data line is fixed at a constant reference voltage. In this case, a constant voltage is written to the storage node regardless of the state of information.
Additionally, the capacitance between the data line and the storage node is exploited to write information to the cell. The voltage of this data line determines the information during the write operation. Before the write word line is activated, the data line is set in an inverse relation to the desired stored voltage value. The word line is subsequently activated and a charge is transferred to the storage node such that it is equalized to the constant voltage of the reference node. After the word line is deactivated, isolating the storage node from the reference voltage node, the data line is restored to its standby state voltage. This change in voltage of the data line causes a change on the storage node due to a capacitive relationship between the data line and the storage node, resulting in information being stored in the cell.
A semiconductor memory cell may achieve a smaller area by sharing the reference node between adjacent cells. In addition, since a constant voltage is written to the storage node, an additional voltage boost circuit for the word line becomes unnecessary, thus reducing the area required by the memory array peripheral circuits. This technique is used in several 2T and 3T memory cell structures presented according to the present invention.
Further, according to at least one embodiment of the present invention, a memory cell with internal gain having a thin-channel transistor is used as the charge transfer element to the storage node. This thin-channel transistor may be fabricated in several ways, but it is defined as having a channel region with a thickness less than or equal to 5 nm. The thin-channel transistor is characterized by a source-drain leakage current of no more than 10xe2x88x9216 Amperes. With this device, a 3-T (3 Transistor) memory cell may be fabricated with a retention time of over 100 times that of conventional cells, thereby making a 3-T cell a plausible solution as a low power dynamic memory.
According to the present invention, a memory is provided in which the memory cell combines the fixed voltage reference node writing method with the thin-channel charge transfer transistor to achieve a high-density, low-power dynamic memory. This memory cell may be fabricated in a 2-T configuration with a double-gate readout transistor and a 3-T cell in which separate storage and read transistors are included in each cell. In addition, a memory derived from the 2-T cell with series-connected memory cells arranged in subcolumns or parallel-connected memory cells arranged in subcolumns is also provided. The present invention results in a density approaching or surpassing that of conventional DRAM memories. Also, memory cells of this type, with an additional capacitive element to increase retention time, are also provided.
In at least one embodiment, a memory comprises a thin-channel transistor used in a memory cell in a four-transistor (4-T) configuration that exhibits a static operation. The memory cell preferably has two access transistors and two thin-channel transistors in a cross-coupling, self-restoring configuration. If the source-drain leakage current from the data line through the bulk transistor is higher than the leakage current from the storage node, a stable memory can be realized, obviating the need for a refresh operation. In addition, the thin-channel transistors may be fabricated in a much smaller area than bulk transistors, realizing a drastically reduced memory cell size. In a further embodiment, a separate two-transistor readout circuit is included in each cell to overcome the slow read time of the four-transistor cell. In this manner, a low power, high-speed memory cell is presented.